Although CMOS integrated circuit devices are often referred to as "semiconductor" devices, such devices are fabricated from various materials which are either electrically conductive, electrically nonconductive or electrically semiconductive. Silicon, the most commonly used semiconductor material can be made conductive by doping it (introducing an impurity into the silicon crystal structure) with either an element such as boron which has one less valence electron than silicon, or with an element such as phosphorus or arsenic which have one more valence electron than silicon. In the case of boron doping, electron "holes" become the charge carriers and the doped silicon is referred to as positive or P-type silicon. In the case of phosphorus or arsenic doping, the additional electrons become the charge carriers and the doped silicon is referred to as negative or N-type silicon. If dopants of opposite type conductivity are used, counter doping will result, and the conductivity type of the most abundant impurity will prevail. Silicon is used either in single-crystal or polycrystalline form. Polycrystalline silicon is referred to hereinafter as "polysilicon" or simply as "poly". Originally, MOS devices were manufactured from metal (used as the transistor gate), semiconductor material (used as the transistor channel material), and oxide (used as the dielectric between the gate and the substrate. Currently, however, most MOS transistors are fabricated using a conductively-doped polycrystalline silicon layer for the gate material.
CMOS processes begin with a lightly-doped P-type or N-type silicon substrate, or lightly-doped epitaxial silicon on a heavily doped substrate. For the sake of simplicity, the prior art CMOS process will be described using P-type silicon as the starting material. If N-type silicon were used, the process steps would be virtually identical, with the exception that in some cases, dopant types would be reversed. Fabrication of sub-micron CMOS devices having a silicided single poly layer and a single metal layer using prior art technology generally requires at least 11 photoresist masks (or simply "photomasks") to create N-channel and P-channel transistors on a silicon substrate (an additional one or two masks is required if lightly-doped drain design is required for both types of transistors). No attempt is made at siliciding source and drain regions in this process. The function of these 11 masks is described below.
The first photoresist mask is used to define N-wells. This is done by creating a first layer of pad oxide on a lightly-doped P-type substrate, depositing a layer of nitride on top of the pad oxide, masking the nitride layer to expose certain regions which are then implanted with arsenic or phosphorus to create the N-wells. The N-well regions are then oxidized using a first conventional LOCOS (LOCal Oxidation of Silicon) step to create a silicon oxide layer to protect them from an optional boron implant which adjusts the concentration of the P-type substrate for the N-channel devices. During the LOCOS process, the pad oxide serves as a stress relief layer. Alternatively, an oxide deposition or oxide growth step could replace the first LOCOS step, eliminating the need for the first pad oxide layer and the first nitride layer. A subsequent high-temperature drive step is used to achieve the desired N-well junction depth. Following removal of the oxide layer, a second layer of pad oxide is grown over the entire wafer. A second silicon nitride layer is then deposited on top of the pad oxide layer.
The second photomask is used to pattern portions of the second silicon nitride layer which define the future active areas on the wafer.
The third photomask is used to cover the N-well regions in order to effect a selective boron field-isolation implant. Following the stripping of the third photomask, the regions on the wafer that are not protected by the remaining portions of the second silicon nitride layer are oxidized to form field oxide regions using a second conventional LOCOS step. The nitride layer is then stripped, as is the pad oxide layer. A layer of sacrificial oxide is then grown to eliminate the "white ribbon" or Kooi effect in the active areas that follows field oxidation. An unmasked implant may be used as a threshold voltage (V.sub.T) adjustment.
The fourth photomask exposes only the channel regions of the N-channel transistors to a high-energy boron punch-through implant. This implant increases both source-to-drain breakdown voltage and the threshold voltage, thus avoiding the short-channel effects which are inherent to nonimplanted, sub-micron N-channel devices. Following the punch-through implant, the fourth photomask is stripped, as is the sacrificial oxide layer. A layer of gate oxide is then grown on all active areas, following which a polysilicon layer is deposited on top of the gate oxide using conventional means (e.g., chemical vapor deposition). The poly layer is then doped with phosphorus, coated with a layer of tungsten silicide by various possible techniques (e.g., chemical vapor deposition, sputtering, or evaporation).
The fifth photomask patterns the silicide-coated polysilicon layer to form the gates of both P-channel and N-channel transistors. Stripping of the fifth photomask is followed by a source/drain oxidation.
The sixth photomask is used to expose only the N-channel source and drain regions to a relatively low-dosage phosphorus implant which creates lightly-doped N- regions. Following the stripping of the sixth mask, a layer of silicon dioxide is deposited on the wafer. An anisotropic etch and a subsequent optional isotropic etch of the silicon dioxide layer leave oxide spacers on the sides of each N-channel and P-channel transistor gate.
The seventh photomask exposes the N-channel source and drain regions to a relatively high-dosage phosphorus or arsenic implant which creates the heavily-doped N+regions. Following the stripping of the seventh mask, the wafer is optionally subjected to elevated temperature for the purpose of diffusing the N-channel implants.
The eighth photomask is used for the high-dosage implantation of either boron or boron difluoride, which creates heavily doped source and drain regions for the P-channel transistors. Following the stripping of the eighth mask, an elevated-temperature drive step is performed, after which the transistors are fully formed. All structures are then covered by an isolation oxide layer.
The ninth photomask is used to define contact vias which will pass through the isolation oxide layer to the poly structures or active area conductive regions below. A deposition of an aluminum metal layer follows.
The tenth photomask is used to pattern the aluminum layer for circuit interconnects. Using a blanket deposition process, the circuitry is covered with one or more passivation layers.
The eleventh photomask defines bonding pad openings which will expose bonding pad regions on the aluminum layer below. This completes the conventional single-poly, single-metal CMOS process.
The business of producing CMOS semiconductor devices is a very competitive, high-volume business. Process efficiency and manufacturability, as well as product quality, reliability, and performance are the key factors that will determine the economic success or failure of such a venture. Each new generation of CMOS devices is expected to be faster and more compact than the generation it replaces. Four-fold density increases from one generation to the next have become standard. If this increase in density is achieved with no increase in die size, device geometries must be more or less halved. As geometries shrink, each photolithographic step becomes more costly. The increase and cost may be attributed to a number of factors, including:
higher capital costs for precision "state-of-the-art" photolithographic equipment;
lowered yields and decreased reliability due to defect density increases invariably associated with each photomasking step;
an increase in the number of processing steps for each mask level, which slows the fabrication process and requires additional expensive equipment;
the requirement for ultra-clean fabrication facilities which are both expensive to construct and expensive to operate;
greater investment per wafer during fabrication, which increases the cost of scrapping defective devices; and
costs associated with the step required subsequent to the masking step, whether it be an implant or an etch.
From the aforementioned discussion, it is evident that the elimination of photomasking steps from a CMOS process will have a direct impact on the cost, reliability, and manufacturability of the product.
A novel process is disclosed in the 1982 Japanese patent issued to Masahide Ogawa (No. 57-17164) for fabricating a CMOS integrated circuit by processing N-channel and P-channel devices separately. As with the conventional CMOS process, a single polysilicon layer is used to form both N-channel and P-channel gates. However, N-channel devices are formed first, with unetched polysilicon left in the future P-channel regions until N-channel processing is complete. The mask used to subsequently pattern the P-channel devices is also used to blanket and protect the already-formed N-channel devices. This process is herein referred to as the split-polysilicon CMOS process. The spilt-polysilicon CMOS process, through largely ignored by semiconductor manufacturers in the U.S. and abroad, holds tremendous potential for reducing photomasking steps in a CMOS process.
A pending U.S. Pat. No. 7/427,639, submitted by Tyler A. Lowrey, Randal W. Chance, and Ward D. Parkinson of Micron Technology, Inc. of Boise, Id. details an improved split-polysilicon CMOS process. The improved CMOS fabrication process is based on the aforementioned split-polysilicon CMOS process developed in Japan by Mashahide Ogawa. The improved process utilizes an unmasked N-channel punchthrough implant and unmasked N-channel source/drain implants that are self-aligned to gate electrodes to create high-performance LDD-type N-channel transistors. These high-performance transistors have both punchthrough regions and LDD-type source/drain regions. By utilizing the split-polysilicon CMOS process in combination with the unmasked implants, the number of masks required to form both N-channel and P-channel devices can be reduced from eleven (for the standard CMOS process) to eight (for the improved process). P-channel source and drain regions, although of conventional non-LDD design, are offset from the edges of the P-channel gates by undercutting the gates beneath the photoresist during the gate-patterning etch. The gate-patterning photoresist is then used as an offsetting implant mask.